HW7: exercise 3.3
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Claudio Maggioni
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131
Homework 7/3.3.circ
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131
Homework 7/3.3.circ
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0"/>
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<lib desc="#Gates" name="1"/>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#Base" name="6">
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<tool name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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</lib>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="6" map="Button2" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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<tool lib="6" map="Button3" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="6" name="Poke Tool"/>
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<tool lib="6" name="Edit Tool"/>
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<tool lib="6" name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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<sep/>
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<tool lib="0" name="Pin">
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<a name="tristate" val="false"/>
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</tool>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="labelloc" val="east"/>
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</tool>
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<tool lib="1" name="NOT Gate"/>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate">
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<a name="size" val="30"/>
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<a name="inputs" val="3"/>
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</tool>
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</toolbar>
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<circuit name="main">
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<a name="circuit" val="main"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="north"/>
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<a name="clabelfont" val="SansSerif plain 12"/>
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<wire from="(240,290)" to="(390,290)"/>
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<wire from="(230,210)" to="(230,250)"/>
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<wire from="(230,210)" to="(300,210)"/>
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<wire from="(320,360)" to="(320,370)"/>
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<wire from="(320,210)" to="(390,210)"/>
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<wire from="(240,280)" to="(240,290)"/>
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<wire from="(300,360)" to="(300,400)"/>
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<wire from="(310,200)" to="(310,330)"/>
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<wire from="(320,200)" to="(320,210)"/>
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<wire from="(320,370)" to="(390,370)"/>
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<wire from="(300,200)" to="(300,210)"/>
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<wire from="(220,280)" to="(220,400)"/>
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<wire from="(310,140)" to="(310,170)"/>
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<comp lib="0" loc="(220,400)" name="Pin">
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<a name="facing" val="north"/>
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<a name="tristate" val="false"/>
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</comp>
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<comp lib="0" loc="(390,290)" name="Pin">
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<a name="facing" val="west"/>
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<a name="tristate" val="false"/>
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</comp>
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<comp lib="6" loc="(475,215)" name="Text">
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<a name="text" val="NEXT_ADDRESS[8]"/>
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</comp>
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<comp lib="6" loc="(219,442)" name="Text">
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<a name="text" val="N"/>
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</comp>
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<comp lib="6" loc="(437,375)" name="Text">
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<a name="text" val="JAMZ"/>
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</comp>
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<comp lib="0" loc="(310,140)" name="Pin">
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<a name="facing" val="south"/>
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<a name="output" val="true"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="1" loc="(310,170)" name="OR Gate">
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<a name="facing" val="north"/>
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<a name="size" val="30"/>
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<a name="inputs" val="3"/>
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</comp>
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<comp lib="0" loc="(300,400)" name="Pin">
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<a name="facing" val="north"/>
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<a name="tristate" val="false"/>
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</comp>
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<comp lib="6" loc="(437,296)" name="Text">
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<a name="text" val="JAMN"/>
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</comp>
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<comp lib="6" loc="(300,441)" name="Text">
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<a name="text" val="Z"/>
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</comp>
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<comp lib="0" loc="(390,210)" name="Pin">
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<a name="facing" val="west"/>
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<a name="tristate" val="false"/>
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</comp>
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<comp lib="1" loc="(310,330)" name="AND Gate">
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<a name="facing" val="north"/>
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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</comp>
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<comp lib="6" loc="(313,109)" name="Text">
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<a name="text" val="HIGH_BIT"/>
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</comp>
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<comp lib="0" loc="(390,370)" name="Pin">
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<a name="facing" val="west"/>
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<a name="tristate" val="false"/>
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</comp>
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<comp lib="1" loc="(230,250)" name="AND Gate">
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<a name="facing" val="north"/>
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<a name="size" val="30"/>
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<a name="inputs" val="2"/>
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</comp>
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</circuit>
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</project>
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Homework 7/3.3.png
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BIN
Homework 7/3.3.png
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