ex 2.4
This commit is contained in:
parent
b01f69fec1
commit
f675fe14dd
1 changed files with 161 additions and 0 deletions
161
CA_2.4_Homework_5.circ
Normal file
161
CA_2.4_Homework_5.circ
Normal file
|
@ -0,0 +1,161 @@
|
||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<project source="2.7.1" version="1.0">
|
||||||
|
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
|
||||||
|
<lib desc="#Wiring" name="0"/>
|
||||||
|
<lib desc="#Gates" name="1"/>
|
||||||
|
<lib desc="#Plexers" name="2"/>
|
||||||
|
<lib desc="#Arithmetic" name="3"/>
|
||||||
|
<lib desc="#Memory" name="4"/>
|
||||||
|
<lib desc="#I/O" name="5"/>
|
||||||
|
<lib desc="#Base" name="6">
|
||||||
|
<tool name="Text Tool">
|
||||||
|
<a name="text" val=""/>
|
||||||
|
<a name="font" val="SansSerif plain 12"/>
|
||||||
|
<a name="halign" val="center"/>
|
||||||
|
<a name="valign" val="base"/>
|
||||||
|
</tool>
|
||||||
|
</lib>
|
||||||
|
<main name="main"/>
|
||||||
|
<options>
|
||||||
|
<a name="gateUndefined" val="ignore"/>
|
||||||
|
<a name="simlimit" val="1000"/>
|
||||||
|
<a name="simrand" val="0"/>
|
||||||
|
</options>
|
||||||
|
<mappings>
|
||||||
|
<tool lib="6" map="Button2" name="Menu Tool"/>
|
||||||
|
<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
|
||||||
|
<tool lib="6" map="Button3" name="Menu Tool"/>
|
||||||
|
</mappings>
|
||||||
|
<toolbar>
|
||||||
|
<tool lib="6" name="Poke Tool"/>
|
||||||
|
<tool lib="6" name="Edit Tool"/>
|
||||||
|
<tool lib="6" name="Text Tool">
|
||||||
|
<a name="text" val=""/>
|
||||||
|
<a name="font" val="SansSerif plain 12"/>
|
||||||
|
<a name="halign" val="center"/>
|
||||||
|
<a name="valign" val="base"/>
|
||||||
|
</tool>
|
||||||
|
<sep/>
|
||||||
|
<tool lib="0" name="Pin">
|
||||||
|
<a name="tristate" val="false"/>
|
||||||
|
</tool>
|
||||||
|
<tool lib="0" name="Pin">
|
||||||
|
<a name="facing" val="west"/>
|
||||||
|
<a name="output" val="true"/>
|
||||||
|
<a name="labelloc" val="east"/>
|
||||||
|
</tool>
|
||||||
|
<tool lib="1" name="NOT Gate"/>
|
||||||
|
<tool lib="1" name="AND Gate"/>
|
||||||
|
<tool lib="1" name="OR Gate"/>
|
||||||
|
</toolbar>
|
||||||
|
<circuit name="main">
|
||||||
|
<a name="circuit" val="main"/>
|
||||||
|
<a name="clabel" val=""/>
|
||||||
|
<a name="clabelup" val="east"/>
|
||||||
|
<a name="clabelfont" val="SansSerif plain 12"/>
|
||||||
|
<wire from="(80,130)" to="(80,190)"/>
|
||||||
|
<wire from="(100,250)" to="(100,300)"/>
|
||||||
|
<wire from="(210,260)" to="(210,270)"/>
|
||||||
|
<wire from="(80,130)" to="(160,130)"/>
|
||||||
|
<wire from="(80,230)" to="(210,230)"/>
|
||||||
|
<wire from="(70,120)" to="(210,120)"/>
|
||||||
|
<wire from="(190,130)" to="(210,130)"/>
|
||||||
|
<wire from="(190,270)" to="(210,270)"/>
|
||||||
|
<wire from="(190,190)" to="(210,190)"/>
|
||||||
|
<wire from="(190,240)" to="(210,240)"/>
|
||||||
|
<wire from="(260,140)" to="(320,140)"/>
|
||||||
|
<wire from="(100,210)" to="(100,250)"/>
|
||||||
|
<wire from="(90,240)" to="(160,240)"/>
|
||||||
|
<wire from="(170,20)" to="(180,20)"/>
|
||||||
|
<wire from="(320,190)" to="(320,240)"/>
|
||||||
|
<wire from="(70,220)" to="(70,270)"/>
|
||||||
|
<wire from="(100,70)" to="(180,70)"/>
|
||||||
|
<wire from="(90,200)" to="(210,200)"/>
|
||||||
|
<wire from="(90,290)" to="(90,310)"/>
|
||||||
|
<wire from="(180,20)" to="(180,70)"/>
|
||||||
|
<wire from="(320,190)" to="(340,190)"/>
|
||||||
|
<wire from="(70,170)" to="(70,220)"/>
|
||||||
|
<wire from="(60,20)" to="(70,20)"/>
|
||||||
|
<wire from="(80,280)" to="(80,310)"/>
|
||||||
|
<wire from="(90,60)" to="(140,60)"/>
|
||||||
|
<wire from="(390,190)" to="(510,190)"/>
|
||||||
|
<wire from="(100,150)" to="(100,210)"/>
|
||||||
|
<wire from="(100,70)" to="(100,110)"/>
|
||||||
|
<wire from="(320,140)" to="(320,190)"/>
|
||||||
|
<wire from="(260,190)" to="(320,190)"/>
|
||||||
|
<wire from="(80,190)" to="(80,230)"/>
|
||||||
|
<wire from="(70,120)" to="(70,170)"/>
|
||||||
|
<wire from="(90,100)" to="(90,140)"/>
|
||||||
|
<wire from="(190,290)" to="(210,290)"/>
|
||||||
|
<wire from="(70,270)" to="(160,270)"/>
|
||||||
|
<wire from="(80,190)" to="(160,190)"/>
|
||||||
|
<wire from="(90,240)" to="(90,290)"/>
|
||||||
|
<wire from="(100,300)" to="(210,300)"/>
|
||||||
|
<wire from="(80,90)" to="(210,90)"/>
|
||||||
|
<wire from="(80,50)" to="(80,90)"/>
|
||||||
|
<wire from="(100,110)" to="(100,150)"/>
|
||||||
|
<wire from="(260,290)" to="(320,290)"/>
|
||||||
|
<wire from="(320,90)" to="(320,140)"/>
|
||||||
|
<wire from="(70,270)" to="(70,310)"/>
|
||||||
|
<wire from="(90,200)" to="(90,240)"/>
|
||||||
|
<wire from="(90,100)" to="(210,100)"/>
|
||||||
|
<wire from="(90,140)" to="(90,200)"/>
|
||||||
|
<wire from="(70,80)" to="(210,80)"/>
|
||||||
|
<wire from="(70,20)" to="(70,80)"/>
|
||||||
|
<wire from="(190,170)" to="(210,170)"/>
|
||||||
|
<wire from="(110,20)" to="(110,50)"/>
|
||||||
|
<wire from="(100,20)" to="(110,20)"/>
|
||||||
|
<wire from="(100,300)" to="(100,310)"/>
|
||||||
|
<wire from="(140,20)" to="(140,60)"/>
|
||||||
|
<wire from="(70,80)" to="(70,120)"/>
|
||||||
|
<wire from="(70,170)" to="(160,170)"/>
|
||||||
|
<wire from="(100,110)" to="(210,110)"/>
|
||||||
|
<wire from="(260,240)" to="(320,240)"/>
|
||||||
|
<wire from="(260,90)" to="(320,90)"/>
|
||||||
|
<wire from="(90,290)" to="(160,290)"/>
|
||||||
|
<wire from="(100,250)" to="(210,250)"/>
|
||||||
|
<wire from="(80,90)" to="(80,130)"/>
|
||||||
|
<wire from="(70,220)" to="(210,220)"/>
|
||||||
|
<wire from="(90,140)" to="(210,140)"/>
|
||||||
|
<wire from="(80,230)" to="(80,280)"/>
|
||||||
|
<wire from="(100,210)" to="(210,210)"/>
|
||||||
|
<wire from="(80,50)" to="(110,50)"/>
|
||||||
|
<wire from="(90,60)" to="(90,100)"/>
|
||||||
|
<wire from="(80,280)" to="(210,280)"/>
|
||||||
|
<wire from="(320,240)" to="(320,290)"/>
|
||||||
|
<wire from="(100,150)" to="(210,150)"/>
|
||||||
|
<comp lib="1" loc="(390,190)" name="AND Gate"/>
|
||||||
|
<comp lib="1" loc="(260,240)" name="OR Gate"/>
|
||||||
|
<comp lib="1" loc="(190,290)" name="NOT Gate"/>
|
||||||
|
<comp lib="0" loc="(170,20)" name="Pin">
|
||||||
|
<a name="tristate" val="false"/>
|
||||||
|
</comp>
|
||||||
|
<comp lib="5" loc="(510,190)" name="LED"/>
|
||||||
|
<comp lib="1" loc="(190,240)" name="NOT Gate"/>
|
||||||
|
<comp lib="1" loc="(190,270)" name="NOT Gate"/>
|
||||||
|
<comp lib="6" loc="(131,44)" name="Text">
|
||||||
|
<a name="text" val="X2"/>
|
||||||
|
</comp>
|
||||||
|
<comp lib="1" loc="(260,140)" name="OR Gate"/>
|
||||||
|
<comp lib="6" loc="(51,43)" name="Text">
|
||||||
|
<a name="text" val="X0"/>
|
||||||
|
</comp>
|
||||||
|
<comp lib="0" loc="(100,20)" name="Pin">
|
||||||
|
<a name="tristate" val="false"/>
|
||||||
|
</comp>
|
||||||
|
<comp lib="0" loc="(60,20)" name="Pin"/>
|
||||||
|
<comp lib="0" loc="(140,20)" name="Pin"/>
|
||||||
|
<comp lib="1" loc="(190,130)" name="NOT Gate"/>
|
||||||
|
<comp lib="1" loc="(260,90)" name="OR Gate"/>
|
||||||
|
<comp lib="1" loc="(260,190)" name="OR Gate"/>
|
||||||
|
<comp lib="6" loc="(161,43)" name="Text">
|
||||||
|
<a name="text" val="X3"/>
|
||||||
|
</comp>
|
||||||
|
<comp lib="1" loc="(190,170)" name="NOT Gate"/>
|
||||||
|
<comp lib="1" loc="(260,290)" name="OR Gate"/>
|
||||||
|
<comp lib="1" loc="(190,190)" name="NOT Gate"/>
|
||||||
|
<comp lib="6" loc="(92,43)" name="Text">
|
||||||
|
<a name="text" val="X1"/>
|
||||||
|
</comp>
|
||||||
|
</circuit>
|
||||||
|
</project>
|
Reference in a new issue