229 lines
6.4 KiB
C
Executable File
229 lines
6.4 KiB
C
Executable File
#include "devices/serial.h"
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#include <debug.h>
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#include "devices/input.h"
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#include "devices/intq.h"
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#include "devices/timer.h"
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#include "threads/io.h"
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#include "threads/interrupt.h"
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#include "threads/synch.h"
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#include "threads/thread.h"
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/* Register definitions for the 16550A UART used in PCs.
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The 16550A has a lot more going on than shown here, but this
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is all we need.
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Refer to [PC16650D] for hardware information. */
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/* I/O port base address for the first serial port. */
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#define IO_BASE 0x3f8
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/* DLAB=0 registers. */
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#define RBR_REG (IO_BASE + 0) /* Receiver Buffer Reg. (read-only). */
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#define THR_REG (IO_BASE + 0) /* Transmitter Holding Reg. (write-only). */
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#define IER_REG (IO_BASE + 1) /* Interrupt Enable Reg.. */
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/* DLAB=1 registers. */
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#define LS_REG (IO_BASE + 0) /* Divisor Latch (LSB). */
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#define MS_REG (IO_BASE + 1) /* Divisor Latch (MSB). */
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/* DLAB-insensitive registers. */
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#define IIR_REG (IO_BASE + 2) /* Interrupt Identification Reg. (read-only) */
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#define FCR_REG (IO_BASE + 2) /* FIFO Control Reg. (write-only). */
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#define LCR_REG (IO_BASE + 3) /* Line Control Register. */
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#define MCR_REG (IO_BASE + 4) /* MODEM Control Register. */
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#define LSR_REG (IO_BASE + 5) /* Line Status Register (read-only). */
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/* Interrupt Enable Register bits. */
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#define IER_RECV 0x01 /* Interrupt when data received. */
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#define IER_XMIT 0x02 /* Interrupt when transmit finishes. */
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/* Line Control Register bits. */
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#define LCR_N81 0x03 /* No parity, 8 data bits, 1 stop bit. */
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#define LCR_DLAB 0x80 /* Divisor Latch Access Bit (DLAB). */
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/* MODEM Control Register. */
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#define MCR_OUT2 0x08 /* Output line 2. */
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/* Line Status Register. */
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#define LSR_DR 0x01 /* Data Ready: received data byte is in RBR. */
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#define LSR_THRE 0x20 /* THR Empty. */
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/* Transmission mode. */
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static enum { UNINIT, POLL, QUEUE } mode;
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/* Data to be transmitted. */
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static struct intq txq;
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static void set_serial (int bps);
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static void putc_poll (uint8_t);
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static void write_ier (void);
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static intr_handler_func serial_interrupt;
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/* Initializes the serial port device for polling mode.
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Polling mode busy-waits for the serial port to become free
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before writing to it. It's slow, but until interrupts have
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been initialized it's all we can do. */
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static void
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init_poll (void)
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{
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ASSERT (mode == UNINIT);
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outb (IER_REG, 0); /* Turn off all interrupts. */
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outb (FCR_REG, 0); /* Disable FIFO. */
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set_serial (9600); /* 9.6 kbps, N-8-1. */
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outb (MCR_REG, MCR_OUT2); /* Required to enable interrupts. */
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intq_init (&txq);
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mode = POLL;
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}
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/* Initializes the serial port device for queued interrupt-driven
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I/O. With interrupt-driven I/O we don't waste CPU time
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waiting for the serial device to become ready. */
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void
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serial_init_queue (void)
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{
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enum intr_level old_level;
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if (mode == UNINIT)
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init_poll ();
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ASSERT (mode == POLL);
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intr_register_ext (0x20 + 4, serial_interrupt, "serial");
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mode = QUEUE;
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old_level = intr_disable ();
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write_ier ();
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intr_set_level (old_level);
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}
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/* Sends BYTE to the serial port. */
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void
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serial_putc (uint8_t byte)
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{
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enum intr_level old_level = intr_disable ();
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if (mode != QUEUE)
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{
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/* If we're not set up for interrupt-driven I/O yet,
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use dumb polling to transmit a byte. */
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if (mode == UNINIT)
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init_poll ();
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putc_poll (byte);
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}
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else
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{
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/* Otherwise, queue a byte and update the interrupt enable
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register. */
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if (old_level == INTR_OFF && intq_full (&txq))
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{
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/* Interrupts are off and the transmit queue is full.
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If we wanted to wait for the queue to empty,
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we'd have to reenable interrupts.
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That's impolite, so we'll send a character via
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polling instead. */
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putc_poll (intq_getc (&txq));
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}
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intq_putc (&txq, byte);
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write_ier ();
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}
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intr_set_level (old_level);
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}
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/* Flushes anything in the serial buffer out the port in polling
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mode. */
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void
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serial_flush (void)
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{
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enum intr_level old_level = intr_disable ();
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while (!intq_empty (&txq))
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putc_poll (intq_getc (&txq));
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intr_set_level (old_level);
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}
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/* The fullness of the input buffer may have changed. Reassess
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whether we should block receive interrupts.
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Called by the input buffer routines when characters are added
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to or removed from the buffer. */
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void
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serial_notify (void)
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{
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ASSERT (intr_get_level () == INTR_OFF);
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if (mode == QUEUE)
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write_ier ();
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}
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/* Configures the serial port for BPS bits per second. */
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static void
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set_serial (int bps)
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{
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int base_rate = 1843200 / 16; /* Base rate of 16550A, in Hz. */
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uint16_t divisor = base_rate / bps; /* Clock rate divisor. */
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ASSERT (bps >= 300 && bps <= 115200);
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/* Enable DLAB. */
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outb (LCR_REG, LCR_N81 | LCR_DLAB);
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/* Set data rate. */
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outb (LS_REG, divisor & 0xff);
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outb (MS_REG, divisor >> 8);
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/* Reset DLAB. */
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outb (LCR_REG, LCR_N81);
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}
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/* Update interrupt enable register. */
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static void
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write_ier (void)
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{
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uint8_t ier = 0;
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ASSERT (intr_get_level () == INTR_OFF);
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/* Enable transmit interrupt if we have any characters to
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transmit. */
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if (!intq_empty (&txq))
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ier |= IER_XMIT;
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/* Enable receive interrupt if we have room to store any
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characters we receive. */
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if (!input_full ())
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ier |= IER_RECV;
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outb (IER_REG, ier);
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}
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/* Polls the serial port until it's ready,
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and then transmits BYTE. */
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static void
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putc_poll (uint8_t byte)
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{
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ASSERT (intr_get_level () == INTR_OFF);
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while ((inb (LSR_REG) & LSR_THRE) == 0)
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continue;
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outb (THR_REG, byte);
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}
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/* Serial interrupt handler. */
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static void
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serial_interrupt (struct intr_frame *f UNUSED)
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{
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/* Inquire about interrupt in UART. Without this, we can
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occasionally miss an interrupt running under QEMU. */
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inb (IIR_REG);
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/* As long as we have room to receive a byte, and the hardware
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has a byte for us, receive a byte. */
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while (!input_full () && (inb (LSR_REG) & LSR_DR) != 0)
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input_putc (inb (RBR_REG));
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/* As long as we have a byte to transmit, and the hardware is
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ready to accept a byte for transmission, transmit a byte. */
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while (!intq_empty (&txq) && (inb (LSR_REG) & LSR_THRE) != 0)
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outb (THR_REG, intq_getc (&txq));
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/* Update interrupt enable register based on queue status. */
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write_ier ();
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}
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