438 lines
14 KiB
C
Executable file
438 lines
14 KiB
C
Executable file
#include "threads/interrupt.h"
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#include <debug.h>
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#include <inttypes.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "threads/flags.h"
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#include "threads/intr-stubs.h"
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#include "threads/io.h"
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#include "threads/thread.h"
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#include "threads/vaddr.h"
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#include "devices/timer.h"
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/* Programmable Interrupt Controller (PIC) registers.
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A PC has two PICs, called the master and slave PICs, with the
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slave attached ("cascaded") to the master IRQ line 2. */
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#define PIC0_CTRL 0x20 /* Master PIC control register address. */
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#define PIC0_DATA 0x21 /* Master PIC data register address. */
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#define PIC1_CTRL 0xa0 /* Slave PIC control register address. */
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#define PIC1_DATA 0xa1 /* Slave PIC data register address. */
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/* Number of x86 interrupts. */
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#define INTR_CNT 256
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/* The Interrupt Descriptor Table (IDT). The format is fixed by
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the CPU. See [IA32-v3a] sections 5.10 "Interrupt Descriptor
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Table (IDT)", 5.11 "IDT Descriptors", 5.12.1.2 "Flag Usage By
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Exception- or Interrupt-Handler Procedure". */
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static uint64_t idt[INTR_CNT];
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/* Interrupt handler functions for each interrupt. */
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static intr_handler_func *intr_handlers[INTR_CNT];
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/* Names for each interrupt, for debugging purposes. */
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static const char *intr_names[INTR_CNT];
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/* Number of unexpected interrupts for each vector. An
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unexpected interrupt is one that has no registered handler. */
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static unsigned int unexpected_cnt[INTR_CNT];
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/* External interrupts are those generated by devices outside the
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CPU, such as the timer. External interrupts run with
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interrupts turned off, so they never nest, nor are they ever
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pre-empted. Handlers for external interrupts also may not
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sleep, although they may invoke intr_yield_on_return() to
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request that a new process be scheduled just before the
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interrupt returns. */
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static bool in_external_intr; /* Are we processing an external interrupt? */
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static bool yield_on_return; /* Should we yield on interrupt return? */
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/* Programmable Interrupt Controller helpers. */
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static void pic_init (void);
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static void pic_end_of_interrupt (int irq);
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/* Interrupt Descriptor Table helpers. */
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static uint64_t make_intr_gate (void (*) (void), int dpl);
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static uint64_t make_trap_gate (void (*) (void), int dpl);
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static inline uint64_t make_idtr_operand (uint16_t limit, void *base);
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/* Interrupt handlers. */
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void intr_handler (struct intr_frame *args);
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static void unexpected_interrupt (const struct intr_frame *);
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/* Returns the current interrupt status. */
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enum intr_level
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intr_get_level (void)
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{
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uint32_t flags;
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/* Push the flags register on the processor stack, then pop the
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value off the stack into `flags'. See [IA32-v2b] "PUSHF"
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and "POP" and [IA32-v3a] 5.8.1 "Masking Maskable Hardware
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Interrupts". */
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asm volatile ("pushfl; popl %0" : "=g" (flags));
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return flags & FLAG_IF ? INTR_ON : INTR_OFF;
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}
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/* Enables or disables interrupts as specified by LEVEL and
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returns the previous interrupt status. */
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enum intr_level
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intr_set_level (enum intr_level level)
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{
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return level == INTR_ON ? intr_enable () : intr_disable ();
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}
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/* Enables interrupts and returns the previous interrupt status. */
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enum intr_level
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intr_enable (void)
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{
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enum intr_level old_level = intr_get_level ();
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ASSERT (!intr_context ());
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/* Enable interrupts by setting the interrupt flag.
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See [IA32-v2b] "STI" and [IA32-v3a] 5.8.1 "Masking Maskable
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Hardware Interrupts". */
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asm volatile ("sti");
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return old_level;
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}
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/* Disables interrupts and returns the previous interrupt status. */
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enum intr_level
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intr_disable (void)
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{
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enum intr_level old_level = intr_get_level ();
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/* Disable interrupts by clearing the interrupt flag.
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See [IA32-v2b] "CLI" and [IA32-v3a] 5.8.1 "Masking Maskable
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Hardware Interrupts". */
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asm volatile ("cli" : : : "memory");
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return old_level;
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}
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/* Initializes the interrupt system. */
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void
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intr_init (void)
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{
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uint64_t idtr_operand;
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int i;
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/* Initialize interrupt controller. */
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pic_init ();
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/* Initialize IDT. */
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for (i = 0; i < INTR_CNT; i++)
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idt[i] = make_intr_gate (intr_stubs[i], 0);
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/* Load IDT register.
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See [IA32-v2a] "LIDT" and [IA32-v3a] 5.10 "Interrupt
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Descriptor Table (IDT)". */
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idtr_operand = make_idtr_operand (sizeof idt - 1, idt);
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asm volatile ("lidt %0" : : "m" (idtr_operand));
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/* Initialize intr_names. */
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for (i = 0; i < INTR_CNT; i++)
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intr_names[i] = "unknown";
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intr_names[0] = "#DE Divide Error";
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intr_names[1] = "#DB Debug Exception";
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intr_names[2] = "NMI Interrupt";
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intr_names[3] = "#BP Breakpoint Exception";
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intr_names[4] = "#OF Overflow Exception";
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intr_names[5] = "#BR BOUND Range Exceeded Exception";
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intr_names[6] = "#UD Invalid Opcode Exception";
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intr_names[7] = "#NM Device Not Available Exception";
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intr_names[8] = "#DF Double Fault Exception";
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intr_names[9] = "Coprocessor Segment Overrun";
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intr_names[10] = "#TS Invalid TSS Exception";
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intr_names[11] = "#NP Segment Not Present";
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intr_names[12] = "#SS Stack Fault Exception";
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intr_names[13] = "#GP General Protection Exception";
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intr_names[14] = "#PF Page-Fault Exception";
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intr_names[16] = "#MF x87 FPU Floating-Point Error";
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intr_names[17] = "#AC Alignment Check Exception";
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intr_names[18] = "#MC Machine-Check Exception";
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intr_names[19] = "#XF SIMD Floating-Point Exception";
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}
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/* Registers interrupt VEC_NO to invoke HANDLER with descriptor
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privilege level DPL. Names the interrupt NAME for debugging
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purposes. The interrupt handler will be invoked with
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interrupt status set to LEVEL. */
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static void
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register_handler (uint8_t vec_no, int dpl, enum intr_level level,
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intr_handler_func *handler, const char *name)
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{
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ASSERT (intr_handlers[vec_no] == NULL);
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if (level == INTR_ON)
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idt[vec_no] = make_trap_gate (intr_stubs[vec_no], dpl);
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else
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idt[vec_no] = make_intr_gate (intr_stubs[vec_no], dpl);
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intr_handlers[vec_no] = handler;
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intr_names[vec_no] = name;
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}
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/* Registers external interrupt VEC_NO to invoke HANDLER, which
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is named NAME for debugging purposes. The handler will
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execute with interrupts disabled. */
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void
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intr_register_ext (uint8_t vec_no, intr_handler_func *handler,
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const char *name)
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{
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ASSERT (vec_no >= 0x20 && vec_no <= 0x2f);
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register_handler (vec_no, 0, INTR_OFF, handler, name);
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}
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/* Registers internal interrupt VEC_NO to invoke HANDLER, which
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is named NAME for debugging purposes. The interrupt handler
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will be invoked with interrupt status LEVEL.
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The handler will have descriptor privilege level DPL, meaning
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that it can be invoked intentionally when the processor is in
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the DPL or lower-numbered ring. In practice, DPL==3 allows
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user mode to invoke the interrupts and DPL==0 prevents such
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invocation. Faults and exceptions that occur in user mode
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still cause interrupts with DPL==0 to be invoked. See
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[IA32-v3a] sections 4.5 "Privilege Levels" and 4.8.1.1
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"Accessing Nonconforming Code Segments" for further
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discussion. */
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void
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intr_register_int (uint8_t vec_no, int dpl, enum intr_level level,
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intr_handler_func *handler, const char *name)
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{
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ASSERT (vec_no < 0x20 || vec_no > 0x2f);
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register_handler (vec_no, dpl, level, handler, name);
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}
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/* Returns true during processing of an external interrupt
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and false at all other times. */
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bool
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intr_context (void)
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{
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return in_external_intr;
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}
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/* During processing of an external interrupt, directs the
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interrupt handler to yield to a new process just before
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returning from the interrupt. May not be called at any other
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time. */
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void
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intr_yield_on_return (void)
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{
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ASSERT (intr_context ());
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yield_on_return = true;
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}
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/* 8259A Programmable Interrupt Controller. */
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/* Initializes the PICs. Refer to [8259A] for details.
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By default, interrupts 0...15 delivered by the PICs will go to
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interrupt vectors 0...15. Those vectors are also used for CPU
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traps and exceptions, so we reprogram the PICs so that
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interrupts 0...15 are delivered to interrupt vectors 32...47
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(0x20...0x2f) instead. */
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static void
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pic_init (void)
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{
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/* Mask all interrupts on both PICs. */
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outb (PIC0_DATA, 0xff);
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outb (PIC1_DATA, 0xff);
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/* Initialize master. */
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outb (PIC0_CTRL, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
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outb (PIC0_DATA, 0x20); /* ICW2: line IR0...7 -> irq 0x20...0x27. */
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outb (PIC0_DATA, 0x04); /* ICW3: slave PIC on line IR2. */
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outb (PIC0_DATA, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
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/* Initialize slave. */
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outb (PIC1_CTRL, 0x11); /* ICW1: single mode, edge triggered, expect ICW4. */
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outb (PIC1_DATA, 0x28); /* ICW2: line IR0...7 -> irq 0x28...0x2f. */
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outb (PIC1_DATA, 0x02); /* ICW3: slave ID is 2. */
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outb (PIC1_DATA, 0x01); /* ICW4: 8086 mode, normal EOI, non-buffered. */
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/* Unmask all interrupts. */
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outb (PIC0_DATA, 0x00);
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outb (PIC1_DATA, 0x00);
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}
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/* Sends an end-of-interrupt signal to the PIC for the given IRQ.
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If we don't acknowledge the IRQ, it will never be delivered to
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us again, so this is important. */
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static void
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pic_end_of_interrupt (int irq)
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{
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ASSERT (irq >= 0x20 && irq < 0x30);
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/* Acknowledge master PIC. */
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outb (0x20, 0x20);
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/* Acknowledge slave PIC if this is a slave interrupt. */
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if (irq >= 0x28)
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outb (0xa0, 0x20);
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}
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/* Creates an gate that invokes FUNCTION.
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The gate has descriptor privilege level DPL, meaning that it
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can be invoked intentionally when the processor is in the DPL
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or lower-numbered ring. In practice, DPL==3 allows user mode
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to call into the gate and DPL==0 prevents such calls. Faults
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and exceptions that occur in user mode still cause gates with
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DPL==0 to be invoked. See [IA32-v3a] sections 4.5 "Privilege
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Levels" and 4.8.1.1 "Accessing Nonconforming Code Segments"
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for further discussion.
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TYPE must be either 14 (for an interrupt gate) or 15 (for a
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trap gate). The difference is that entering an interrupt gate
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disables interrupts, but entering a trap gate does not. See
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[IA32-v3a] section 5.12.1.2 "Flag Usage By Exception- or
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Interrupt-Handler Procedure" for discussion. */
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static uint64_t
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make_gate (void (*function) (void), int dpl, int type)
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{
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uint32_t e0, e1;
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ASSERT (function != NULL);
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ASSERT (dpl >= 0 && dpl <= 3);
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ASSERT (type >= 0 && type <= 15);
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e0 = (((uint32_t) function & 0xffff) /* Offset 15:0. */
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| (SEL_KCSEG << 16)); /* Target code segment. */
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e1 = (((uint32_t) function & 0xffff0000) /* Offset 31:16. */
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| (1 << 15) /* Present. */
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| ((uint32_t) dpl << 13) /* Descriptor privilege level. */
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| (0 << 12) /* System. */
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| ((uint32_t) type << 8)); /* Gate type. */
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return e0 | ((uint64_t) e1 << 32);
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}
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/* Creates an interrupt gate that invokes FUNCTION with the given
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DPL. */
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static uint64_t
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make_intr_gate (void (*function) (void), int dpl)
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{
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return make_gate (function, dpl, 14);
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}
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/* Creates a trap gate that invokes FUNCTION with the given
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DPL. */
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static uint64_t
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make_trap_gate (void (*function) (void), int dpl)
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{
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return make_gate (function, dpl, 15);
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}
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/* Returns a descriptor that yields the given LIMIT and BASE when
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used as an operand for the LIDT instruction. */
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static inline uint64_t
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make_idtr_operand (uint16_t limit, void *base)
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{
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return limit | ((uint64_t) (uint32_t) base << 16);
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}
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/* Interrupt handlers. */
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/* Handler for all interrupts, faults, and exceptions. This
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function is called by the assembly language interrupt stubs in
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intr-stubs.S. FRAME describes the interrupt and the
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interrupted thread's registers. */
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void
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intr_handler (struct intr_frame *frame)
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{
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bool external;
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intr_handler_func *handler;
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/* External interrupts are special.
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We only handle one at a time (so interrupts must be off)
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and they need to be acknowledged on the PIC (see below).
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An external interrupt handler cannot sleep. */
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external = frame->vec_no >= 0x20 && frame->vec_no < 0x30;
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if (external)
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{
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ASSERT (intr_get_level () == INTR_OFF);
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ASSERT (!intr_context ());
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in_external_intr = true;
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yield_on_return = false;
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}
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/* Invoke the interrupt's handler. */
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handler = intr_handlers[frame->vec_no];
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if (handler != NULL)
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handler (frame);
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else if (frame->vec_no == 0x27 || frame->vec_no == 0x2f)
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{
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/* There is no handler, but this interrupt can trigger
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spuriously due to a hardware fault or hardware race
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condition. Ignore it. */
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}
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else
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unexpected_interrupt (frame);
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/* Complete the processing of an external interrupt. */
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if (external)
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{
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ASSERT (intr_get_level () == INTR_OFF);
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ASSERT (intr_context ());
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in_external_intr = false;
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pic_end_of_interrupt (frame->vec_no);
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if (yield_on_return)
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thread_yield ();
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}
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}
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/* Handles an unexpected interrupt with interrupt frame F. An
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unexpected interrupt is one that has no registered handler. */
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static void
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unexpected_interrupt (const struct intr_frame *f)
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{
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/* Count the number so far. */
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unsigned int n = ++unexpected_cnt[f->vec_no];
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/* If the number is a power of 2, print a message. This rate
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limiting means that we get information about an uncommon
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unexpected interrupt the first time and fairly often after
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that, but one that occurs many times will not overwhelm the
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console. */
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if ((n & (n - 1)) == 0)
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printf ("Unexpected interrupt %#04x (%s)\n",
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f->vec_no, intr_names[f->vec_no]);
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}
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/* Dumps interrupt frame F to the console, for debugging. */
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void
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intr_dump_frame (const struct intr_frame *f)
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{
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uint32_t cr2;
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/* Store current value of CR2 into `cr2'.
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CR2 is the linear address of the last page fault.
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See [IA32-v2a] "MOV--Move to/from Control Registers" and
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[IA32-v3a] 5.14 "Interrupt 14--Page Fault Exception
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(#PF)". */
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asm ("movl %%cr2, %0" : "=r" (cr2));
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printf ("Interrupt %#04x (%s) at eip=%p\n",
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f->vec_no, intr_names[f->vec_no], f->eip);
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printf (" cr2=%08"PRIx32" error=%08"PRIx32"\n", cr2, f->error_code);
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printf (" eax=%08"PRIx32" ebx=%08"PRIx32" ecx=%08"PRIx32" edx=%08"PRIx32"\n",
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f->eax, f->ebx, f->ecx, f->edx);
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printf (" esi=%08"PRIx32" edi=%08"PRIx32" esp=%08"PRIx32" ebp=%08"PRIx32"\n",
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f->esi, f->edi, (uint32_t) f->esp, f->ebp);
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printf (" cs=%04"PRIx16" ds=%04"PRIx16" es=%04"PRIx16" ss=%04"PRIx16"\n",
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f->cs, f->ds, f->es, f->ss);
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}
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/* Returns the name of interrupt VEC. */
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const char *
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intr_name (uint8_t vec)
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{
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return intr_names[vec];
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}
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